1. Field of the Invention
This invention relates to semiconductor design and more specifically to yield analysis for manufacturing of semiconductor designs.
2. Description of the Relevant Art
In deep submicron processes, the issue of achieving reasonable yield in light of manufacturing variability is a considerable challenge. At approximately the 130 nm process node, the underlying physics and quantum mechanical effects begin to govern the behavior of CMOS technology and the ability to dictate and predict the desired behavior begins to decline. In such technologies, channel dopants are in concentrations on the order of fewer than 100 atoms with uncontrollable fluctuations from one device to another; line-width Cd-Variation becomes nearly impossible to control despite recent advances in lithography techniques; leakage is unlike anything seen before; and electrons exhibit direct tunneling through dielectrics as if they were not even there, for example.
In addition to these limitations of solid state device physics, manufacturing technologists face other difficulties in fabricating circuit structures, as evidenced by fabrication topics of late: Ultra-deep ultra-violet lithography, Optical Phase Correction (OPC), Stepper Control, Phase Shift Masks (PSM), Chemical Mechanical Polishing (CMP), Depth of Field correction (DOF), immersion lithography, etc.
These issues add up to uncertainty, variation, and great difficulty in controlling and managing the manufacturing process, which can result in tremendous yield loss. One solution is to implement Monte Carlo based simulation to model and predict yields, and then to make changes to improve yield. This is a reasonable approach but is greatly limited to smaller circuits that may not represent the semiconductor device (e.g., a microprocessor) as a whole. To address this issue, quite often analysts will derive “general-purpose” process corners at which to simulate a design for yield analysis and/or prediction. These general-purpose corners are often non-physical and/or unrealistic, and may not explore the sensitivities that are critical to the metrics of concern for a given circuit or circuit path.
Each circuit and each circuit metric may have its own sensitivities to process, temperature, voltage, signal and other environmental conditions. If these sensitivities all align, they can be systematically offset to improve yield. If not, achieving a reasonable yield becomes a trade-off exercise, which could be so severe as to produce a non-overlapping zero-yielding solution. For example, when manufacturing engineers try to improve the yield by shifting the process, they may improve a circuit-A (or their parametric probe data) but at the cost of hindering a circuit-B. For example, there may be a process condition at which a data-path of a microprocessor will yield well, but a Level 2 Cache in the same microprocessor will not. As the process is offset or shifted to accommodate the Level 2 Cache yield, the data-path yield may start to decline. Therefore, the fact that a wafer satisfies parametric yield (which makes manufacturing engineers happy), does not mean that all the circuits contained on the wafer will likewise yield reasonably well (which makes design engineers sad). All probed parametric measurements and behavior characteristics must simultaneously yield well for the product to yield well.
Using prior art methods, simulations were only done in isolation and could only assess yield for individual circuit metrics. Likewise, process corners were derived only for individual process parameters and often these corners did not represent the actual worst-case conditions as they pertained to circuit metrics. Therefore, prior art solutions often fail to identify sensitivities and critical aspects as they pertain to a particular individual circuit and to an entire semiconductor device as a whole.